Senior ASIC Design Engineer

Location(s):
Boise, Idaho, United States of America
Vancouver, Washington, United States of America
Category: Engineering
Job ID: 3068759
Posted: 12/22/2020 8:00:00 AM

HP is the world’s leading printing company. We are looking for innovators who are ready to make a purposeful impact.  You will be a member of the R&D digital Application-Specific Integrated Circuit (ASIC) design team that develops the main controller with critical HP proprietary intellectual property that separates HP printers from the rest of the competitions. You will work with internal and external partners to deliver industry-leading embedded solutions for future HP printers. 

Responsibilities:

  • Lead functional blocks and/or subsystems of digital ASICs from design to silicon verification. This includes RTL coding, verification, silicon validation, and qualification.

  • Proactively work with other team members and partners to align on specifications, drive reviews, and complete documentation.

  • Manage and expand relationships with internal and external development partners.

  • Be a key contributor to ASIC roadmaps and future innovation.

  • Lead cross-discipline task force to triage product HW & FW integration issues to deliver robust solutions.

  • Contribute to key areas of Inkjet and Laserjet print architecture and data path requirements.

  • Be a key contributor to co-development activities to help prototype ASIC designs in FPGA or other software models to support pre-silicon firmware development and verification.

  • Drive design methodology and tool automation work as needed.

Education and Experience Required:

  • BS or MS degree in electrical engineering or equivalent with focus on VLSI design experience

  • Minimum of 10 years of ASIC or SOC design and development experience

Knowledge and Skills:

  • Deep knowledge of submicron semiconductor technology.

  • Deep knowledge of embedded system design, verification, and product development lifecycle.

  • Very familiar with digital ASIC/SOC design flow from RTL to silicon characterization

  • Very familiar with Synopsys and Cadence EDA tools for Simulation, Synthesis, Timing (STA), Formal and Assertion based verification, etc.

  • Very familiar with design and programming languages: Verilog, SV, Python, Perl, C, C++, etc.

  • Very familiar with code base management method including subversion, git, GitHub, etc.

  • Excellent analytical and problem-solving skills.

  • Excellent written and verbal communication skills, ability to negotiate design features and options

  • Working knowledge of electronic components, PCA designs and use of test equipment

Deep knowledge and domain know-hows in one or more areas below is a big plus.

  • Memory and storage subsystem (DDR, Flash, eMMC, etc.)

  • Xilinx FPGA design methodology

  • Design database management, scripting and other design flow automation

  • Ethernet HW and industry standard High-Speed IO IPs for embedded system.

  • ARM microprocessor subsystem

  • Security subsystem validation in embedded system

  • Inkjet or Laserjet printing technology

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